Logicworks vs vivado12/18/2023 ![]() Xilinx's staff suggests that, in this case, you should find the wire on the schematic (the name it gave to the wire wasn't one I had given to any wires). (Didn't find it, many hours wasted.) Googling sent me to Xilinx's forum. Indeed, I had resorted to "Voodoo hardware" (fix what isn't broken, just to see if anything changes) to see if I could find the bug. The problem turned out to be a single problem, it's just that the wires/nets Vivado pointed me to weren't anywhere near where the error was. Vivado told me I had two problems: a timing loop, and a multiply defined variable. To start off the discussion, please allow me to share that I just spent yesterday and today looking for a problem in my own code, given one of Vivado's cryptic error messages. Likewise, while my work has been very much Verilog focused, I have no criticisms for anyone using VHDL. I believe the issue is open for discussion and debate. The only program above that requires a license to use is Vivado, although some of the above are released under GPLįurther, while I am solidly pro-open source, I am not religiously open source. ( GCC for compiling programs for the ZipCPU) ZipCPU, as an alternative to MicroBlaze (or even NiOS2, OpenRISC, picorv, etc).While the program is designed to load ZipCPU ELF files, there's only two internal constants that restrict it to ZipCPU programs. that have an initial load on them already. zipload: to load programs (ELF files), and sometimes bit files, onto FPGA's.I also use wbicapetwo to switch between FPGA designs contained on my flash. I use this after Vivado has placed an initial load onto my FPGA's. wbprogram: to program bit files onto FPGA's.Vivado: for synthesis, implementation, and any necessary JTAG programming (Requires a UART to wishbone bus converter, or some other way to communicate with a wishbone bus within your design. wbscope (or its companion, wbscopc): for any internal debugging I need to do.yosys: Because 1) it's open source, and 2) it supports some (the iCE40 on my icoboard), though not all, of the hardware I own.GTKWave: for viewing waveform ( VCD) files.Further, it's easy to integrate C++ hardware co-simulations into the result to the extent that I can simulate entire designs ( QSPI flash, VGA displays, OLEDrgb displays, simulated UART's forwarded to TCP/IP ports, etc) using Verilator and (while it might be possible) I don't know how to do that with any other simulation tool. Pro's: compiling a project via Verilator, and finding synthesis errors, can be done in seconds, vice minutes with Vivado. ![]() (Read about my debugging philosophy here, or how you can use Verilator here.) Drawbacks: Verilator is Verilog and System Verilog only, and things the Verilate don't always synthesize using Vivado. Verilator: for simulating anything from individual components (such as this UART), to entire designs (such as my Arty design, CMod S6 design, XuLA2-LX25 design, or even my basic ZipCPU design).I'd like to continue an ongoing discussion that's now taken place across many forum threads, but I'd like to offer for everyone a simple place to put it that.
0 Comments
Leave a Reply.AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |